![]() ![]() The MXR (Make eXecutable Readable) bit modifies the privilege with which loadsĪccess virtual memory. 4.1.1.2 Memory Privilege in sstatus Register For example, when UXLEN=32Īnd SXLEN=64, user-mode memory accesses reference the lowest 4 GiB If UXLEN < SXLEN, user-mode instruction-fetch addresses and load and storeĮffective addresses are taken modulo 2 UXLEN. Results to fill the widest supported XLEN in the destination register. Source register operand bits above the configured XLEN, and must sign-extend If UXLEN ≠ SXLEN, instructions executed in the narrower mode must ignore In particular, an implementation may make UXL be a read-only field whose SXLEN=64, it is a WARL field that encodes the current value of UXLEN. When SXLEN=32, the UXL field does not exist, and UXLEN=32. TheĮncoding of UXL is the same as that of the MXL field of misa, shown in Which may differ from the value of XLEN for S-mode, termed SXLEN. The UXL field controls the value of XLEN for U-mode, termed UXLEN, 4.1.1.1 Base ISA Control in sstatus Register Sstatus is equivalent to reading or writing the homonymous field In a straightforward implementation, reading or writing any field in The sstatus register is a subset of the mstatus register. When an SRET instruction isĮxecuted, SIE is set to SPIE, then SPIE is set to 1. Mode, SPIE is set to SIE, and SIE is set to 0. The SPIE bit indicates whether supervisor interrupts were enabled prior to ![]() Individual interrupt sources using the sie CSR. ![]() When the hart is running in user-mode, the value in SIE is ignored, and When SIE is clear, interrupts are not taken while in supervisor mode. The SIE bit enables or disables all interrupts in supervisor mode. Privilege level is set to user mode if the SPP bit is 0, or supervisor mode if (see Section ) is executed to return from the trap handler, the Originated from user mode, or 1 otherwise. When a trap is taken, SPP is set to 0 if the trap The SPP bit indicates the privilege level at which a hart was executing beforeĮntering supervisor mode. Supervisor-mode status register ( sstatus) when SXLEN=64. Supervisor-mode status register ( sstatus) when SXLEN=32. Register keeps track of the processor’s current operating state. The sstatus register is an SXLEN-bit read/write registerįormatted as shown in Figure 1.1 when SXLEN=32 and 4.1.1 Supervisor Status Register ( sstatus) Many supervisor CSRs are a subset of the equivalent machine-mode CSR,Īnd the machine-mode chapter should be read first to help understand Levels (machine level or other) visible in the CSRs accessible by the Information about the existence (or non-existence) of higher privilege The supervisor should only view CSR state that should be visible to a RISC-V Privileged Instruction Set Listings Platform-Level Interrupt Controller (PLIC) Svinval Standard Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0 Svpbmt Standard Extension for Page-Based Memory Types, Version 1.0 Svnapot Standard Extension for NAPOT Translation Contiguity, Version 1.0 Sv57: Page-Based 57-bit Virtual-Memory System Sv48: Page-Based 48-bit Virtual-Memory System Sv39: Page-Based 39-bit Virtual-Memory System Sv32: Page-Based 32-bit Virtual-Memory Systems Supervisor Memory-Management Fence Instruction Supervisor Address Translation and Protection ( satp) Register Supervisor Environment Configuration Register ( senvcfg) Supervisor Exception Program Counter ( sepc) Supervisor Timers and Performance Counters Supervisor Interrupt Registers ( sip and sie) Supervisor Trap Vector Base Address Register ( stvec) ![]()
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